The present invention is directed to semiconductor devices and, more specifically, to thyristor-based memory.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology may now permit single-die microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second, to be packaged in relatively small semiconductor device packages. As the use of these devices has become more prevalent, the demand for faster operation and better reliability has increased.
An important part in the circuit design, construction, and manufacture of semiconductor devices concerns semiconductor memories; the circuitry used to store digital information. Conventional random access memory devices may include a variety of circuits, such as SRAM and DRAM circuits. SRAMs are mainly used in applications that require a high random access speed and/or a CMOS logic compatible process. DRAMs, on the other hand, are mainly used for high-density applications where the slow random access speed of DRAM can be tolerated.
Some SRAM cell designs may consist of at least two active elements, one of which may include an NDR (Negative Differential Resistance) device. Overall performance of this type of SRAM cell may be based in large part upon the properties of the NDR device. A variety of NDR devices have been introduced in various applications, which may include a simple bipolar transistor or a complicated quantum-effect device. One advantage of an NDR-based cell for an SRAM design may be its potential for allowing a cell area smaller than conventional SRAM cells (such as the 4 T or 6 T cells). Many of the typical NDR-based SRAM cells, however, may have deficiencies that may prohibit their use in some commercial SRAM applications. Some of these deficiencies may include: high power due to the large standby current for its data retention states; excessively high or excessively low voltage levels for cell operation; and/or sensitivity to manufacturing variations which may degrade its noise immunity; limitations in access speed; limited operability over a given temperature range and limited yield due to a variety of fabrication tolerances.
Recently, thyristors have been introduced as a type of NDR device for forming a thyristor-based memory device. These types of memory can potentially provide the speed of conventional SRAM but with the density of DRAM and within a CMOS compatible process. Typically, such thyristor-based memory may comprise a thin capacitively coupled thyristor (“TCCT”) to form a bi-stable element for an SRAM cell. For more details for specific examples of this new device, reference may be made to: “A Novel High Density, Low Voltage SRAM Cell With A Vertical NDR Device,” VLSI Technology Technical Digest, June, 1998; “A Novel Thyristor-based SRAM Cell (T-RAM) for High-Speed, Low-Voltage, Giga-Scale Memories,” International Electron Device Meeting Technical Digest 1999, and “A Semiconductor Capacitively-Coupled NDR Device And Its Applications For High-Speed High-Density Memories And Power Switches,” PCT Int'l Publication No. WO 99/63598, corresponding to U.S. patent application Ser. No. 09/092,449, now U.S. Pat. No. 6,229,161. Each of these documents is hereby incorporated by reference in its entirety.
An important design consideration in any type of thyristor-based memory cell, including the TCCT-based RAM cell, is the holding current of the thyristor. Ideally, the holding current of the thyristor may be designed for a low nominal level for low power while maintaining a stable conducting state for data retention.
Another important consideration of a thyristor-based memory cell is its blocking state. Ideally, the thyristor may be immune to various environmental conditions such as temperature. By such immunity, the thyristor may obtain improved data reliability over temperature.
Further, during manufacture of semiconductor memory, various processes—i.e., such as doping, implant, activation and anneal procedures to name a few—have tolerances or variation, which in turn may impact performance of the device. Accordingly, these variations may impact holding current and/or the blocking level of the thyristor, and, at the same time, affect its reliability for data retention.